Single Channel Core

product brief

 
   
   
   
   

 
 

Multi-Channel Core

product brief

 
     
   
 


 
 
 
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Overview  

The Cores implements standard 40Geth scrambler and descrambler, the 64b/66b encoder and decoder, multi-lane distribution (MLD), alignment marker insertion/striping and block synchronization.

The MLD module distributes data across 4 virtual lanes. The 4 virtual lanes are then transferred on 4x 10Gbps (40Geth) serial lanes, on 2x 20/25Gbps (40/50Geth) serial lanes or on 1x 25Gbps (25Geth) serial lane. On receive, the MLD deskews the physical lanes producing an aligned 40Geth or 50Geth data stream. In 25Geth mode, the MLD just re-aligns the serial data stream.

The Cores optionally support the IEEE Clause 74 Firecode FEC and/or the IEEE Clause 91 Reed Solomon FEC (RS-FEC). The RS-FEC is used for 25 and 50Geth backplane applications over 25Gbps Serdes Lanes. On the application side, the Cores implement a 64-Bit XLGMII (40 Gigabit Media Independent Interface).

On the line side, the Cores implement a flexible 16, 20, 32 or 64 bit parallel interface per lane. Each lane is connectable to Industry standard embedded 10.3125Gbps and 25.78125Gbps Serdes macros.

The PCS Cores can be used with MorethanIP Link Training and Autonegotiation Cores to design flexible backplane interconnection solutions. The MorethanIP Autonegotiation Core is fully generic and can support any proprietary ‘Next Page’ negotiations for selecting the 25Geth or 50Geth modes of operation.

The Multi-Channel Core can be programmed with registers to support the following interface configurations:


Interface
Number of Interfaces

25Geth
4

40Geth
1

50Geth
2

 



 
Relevant products...

4-Lane 10/40 Geth Hydra Core


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Phone:
+49 (0) 8131 333939 0
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+49 (0) 8131 333939 1