Hydra - Multi-Rate
and Multi-Channel Designs
 

 
  4-Lane 10/40
Geth Hydra Core
 
     
  4-Lane 10/40/100
Geth Hydra Core
 
     
  12-Lane 10/40/100
Geth Hydra Core
 

 
 


 
     
   
 


 
 
 
  Member of  
   
       
 
Overview open

In the continuous development of the IEEE for Ethernet lays the foundations for highly scalable and yet well defined networking infrastructures adopted by many industries. One of the major achievements is Ethernet's scalability in supporting applications from low rate consumer and home environments to the highest performance telecom backbone and storage networks. This flexibility however calls for the system architect to choose the right compromise between integration complexity, application support, scalability, new standards support and, eventually, time and risk for product development. MorethanIP provides Cores for each Ethernet speed from 10Mbps to 100Gbps and, with the Ethernet Hydra Core, multi-rate solutions that are field configurable to operate at any rate. The family of Multi-Channel Multi-Rate Hydra Cores is extensible and customizable with the following predefined solutions available addressing different interfaces and implementation tradeoffs:

  • 4-Lane 10/40 Geth Hydra Core:
    Support rates from 10Mbps to 40Gbps with SGMII, XFI and XLAUI,
    available for FPGA and ASIC implementations.
  • 4-Lane 10/40/100 Geth Hydra Core:
    Support rates from 10Mbps to 100Gbps with SGMII, XFI, XLAUI,
    4-Lane CAUI-4 only available for ASIC implementations.
  • 12-Lane 10/40/100 Geth Hydra Core:
    Support rates from 10Mbps to 100Gbps with SGMII, XFI, XLAUI,
    and 10-Lane CAUI only available for ASIC implementations.
    Optionally, a proprietary 120Gbps 12-Lane CXXAUI interface
    can be implemented.

Using the Hydra Cores, companies can maximize important ASIC NRE costs and develop products for today, tomorrow and legacy markets. The Hydra Cores are available and silicon proven in different process nodes as well as in FPGA designs and provides low-risk high value solutions for ASSP, ASIC or FPGA applications.

Ultimate Flexibility open

The Hydra Cores are segmented and are dynamically configurable with registers to select different combinations of data rates and interfaces.

The supported interface options for the different Hydra Cores are listed in the following Tables.

Figure 1: 4-Lane 10/40Geth Hydra Core Interface Options

Interface Mode Number of
10Geth* Ports
Number of
40Geth Ports
1 4 0
2 0 1

Figure 2: 4-Lane 10/40/100Geth Hydra Core Interface Options

Interface Mode Number of
10Geth* Ports
Number of
40Geth Ports
Number of
100Geth Ports
1 4 0 0
2 0 1 0
3 0 0 1

Figure 3: 12-Lane 10/40/100Geth Hydra Core Interface Options

Interface Mode Number of
10Geth*
Ports
Number of
40Geth
Ports
Number of
100Geth
Ports
Number of
120Geth
Ports
1 12 0 0 0
2 8 1 0 0
3 4 2 0 0
4 0 3 0 0
5 2 0 1 0
6 0 0 0 1

 

Complete Feature Set open

The Hydra Cores implement a wide range of networking application support like:
  • IEEE 1588
  • IEEE 802.1as (AVB)
  • IEEE 802.3az, Energy Efficient Ethernet (EEE)
  • IEEE 802.1Qbb Priority-based Flow Control (PFC)
  • IEEE 802.3ap Backplane Ethernet (1000Base-KX, 10GBase-KR and 40GBase-KR4/CR4) with Auto-Negotiation, Link Training and Forward Error Correction (FEC) options
  • Ethernet in First Mile (EFM) and Custom Preamble

MorethanIP is committed to support new standards such as EEE for 40Geth and 100Geth or IEEE802.3bj for 100Geth Backplane application.

The Hydra Cores are optimized for low latency with minimal Frame delay variation.

MorethanIP has also developed a 12-Lane extension of its 100Geth PCS to support 120Gbps applications and provide additional bandwidth, for example, to transfer Frames tagged with proprietary headers.

IEEE1588 Support open

The Hydra Cores support frame Timestamping on incoming and outgoing Timing frames.

The Timestamping function is protocol independent and can then be used to implement precise time synchronization in, for example, IEEE 1588 Precision Time Protocol (PTP), IEEE 802.1as AVB (Audio Video Broadcast, AVB) or other timing protocols.

For a maximum precision, Timestamps are generated with low jitter to meet stringent Telecom application requirements.

The Hydra Cores support 2-step applications whereas the Core generates to the system a timestamp for each timing frame. The system should then use the timestamp to generate and send a follow-up frame.

An optional module is also available for 1-step 1588 applications. The 1-Step module can be used to automatically update, on-the-fly, the timing fields in the outgoing frames.

As a 1588 network may use Timing information over Layer 2 Typed Frames, over UDP/IPv4 or over UDP/IPv6, the 1-Step module also performs automatic CRC and UDP checksum correction.

The 1-Step variant can be used to reduce application and network overhead.

The Hydra Cores, with or without the 1-Step module, can be used to implement any IEEE PTP applications as described in the Table below.

PTP applications

 

Hydra Standard support

Hydra support with optional
1-Step module

Notes

IEEE 1588
PTP

Master Clock

2-Step

2-Step & 1-Step

 

Slave Clock

2-Step

2-Step & 1-Step

 

Boundary Clock

2-Step

2-Step & 1-Step

 

End-to-End (E2E) Transparent Clock

2-Step

2-Step & 1-Step

 

Peer-to-Peer (P2P)
Transparent Clock

2-Step

2-Step & 1-Step

 

IEEE 802.1
as AVB

Master Clock

2-Step

2-Step

AVB uses 2-step for all clocks, hence not requiring the 1-step module

Technology Friendly Solutions open

The Hydra Cores are designed for ease of use and ease of integration in large ASIC or FPGA devices.

The PMA line clocks, generated by the peripheral Serdes blocks, only drive a very small portion of the Core while the majority of the Core logic runs on a single clock domain (System Clock).

The system clock does not need to be changed when the Core mode of operation is switched, for example, from 100Geth to multiple 40Geth or to multiple 10Geth ports.

The system clock can also be generated from any free running oscillator and does not need to be frequency locked with any of the line or application clocks.

The Hydra solution therefore simplifies the chip level clock distribution and eliminates any clock muxing elements or PLLs that are typically used in multi-rate designs to create multiple frequency locked clocks with precise frequency.

These methods together, provide Cores that are easy to integrate and can be freely placed with any form factor.
Hydra Selector Guide open

Application
Rate Support

Line Side/
PHY Technology

4-Lane
10/40
Geth Hydra

4-Lane
10/40/100
Geth Hydra

12-Lane
10/40/100
Geth Hydra

10/100/1000Mbps 1000Base-X X X X
1000Base-KX X X X
SGMII X X X
10Geth 10GBase-R (XFI) X X X
10GBase-KR X X X
40Geth  40GBase-R
(XLAUI)
X X X
40GBase-KR4 X X X
100Geth 100GBase-R
10-Lane CAUI
- - X
100GBase-R
4-Lane CAUI-4
- X -
120Geth Note! 100GBase-R
12-Lane CXXAUI
- - X
FEC (Clause 74) Note! X X X
EEE(802.3az) Note! 1G/10G X X (X)
IEEE1588 Two-Step X X X
One-Step Note! X X X
Flow Control Link Level X X X
PFC X X X
FPGA X - -
ASIC X X X
Customer Specific Solutions open

The standard Hydra Cores can be modified by modified by MorethanIP, for example, to change the number of Lanes or add different line interfaces such as QSGMII or XAUI. MorethanIP can also add customer specific features.
 
Relevant products...
100/40 Gigabit Etnernet

10G Anyspeed MAC

Quick Contact
for additonal Questions
Phone:
+49 (0) 8131 333939 0


E-Mail:
info@morethanip.com

Contact
MorethanIP GmbH
E-Mail · Internet

Europe

Münchner Str. 199
D-85757 Karlsfeld
Germany

Phone:
+49 (0) 8131 333939 0
FAX:
+49 (0) 8131 333939 1

 

 

   
   
   
   
   
   
   
   

 

 

40G/100G pending standardization
License Option