MLG 1.0 PCS Core  
   

 
 

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Introduction open

The Multi-Link Gearbox (MLG) functionality is defined by the OIF Multi-link Gearbox Implementation Agreement (OIF-MLG-01.0, May 2012).

The MLG interface multiplexes ten 10GBase-R PCS channels into a single 100Gbps link compatible with the IEEE 802.3ba Clause 82 100Gbps Ethernet CAUI-4 interface.

On Transmit, the MLG Core creates a datastream of 20 VLs (Virtual Lanes), adds the MLG markers and bit-muxes the VLs into four 25G Serdes interfaces.

On Receive, the MLG Core performs bit demuxing, lane alignment, marker termination and VL reordering to recreate 10 independent 10GBase-R streams.

To compensate for the bandwidth overhead from the MLG markers insertion, the Core, on Transmit, removes XGMII Idle columns, on each 10GBase-R stream.

The Core implements the ten 10GBase-R PCS functions and provides per channel a 32-bit XGMII for direct interconnect with 10G Ethernet MACs.

For management and configuration a 16-Bit de-multiplexed register interface allows accessing each individual channel.

The core is delivered in generic Source Verilog synthesizable HDL code and is provided with a comprehensive verification environment.

Product Information:

The MLG 1.0 Core is also available integrated in the  MorethanIP 10/40/100Geth Multi-Rate Multi-Lane Core.



 
Relevant products...
4-Lane 10/40
Geth Hydra Core


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